1. Field of the Invention
This invention relates to the interfacing of high speed, low voltage, data streams with CMOS circuits and, more specifically, to converting low voltage, differential, ECL signal levels to higher voltage levels which are compatible with CMOS circuits while maintaining high speed and sufficient drive capability.
2. Brief Description of the Prior Art
Differential Emitter Coupled Logic (ECL) circuitry is often used in high speed data transmission applications due to its small signal nature and resulting higher speed of operation. The differential aspect of these low level signals provides improved signal-to-noise, due to common mode operation at the receiving end of the transmission. However, it is important that these low level ECL signals be converted to higher levels without a significant degradation in speed and that the output of the converter has sufficient drive capability to make it useful for a particular application.
Existing circuits of this type often make the ECL to CMOS level conversion at the expense of speed and/or drive capability. Inherently, the lower ECL levels can be switched faster than the larger CMOS levels, but attempts to speed up the conversion process often diminish the output drive capability of the circuit. Representative prior circuits of this general type are shown in U.S. Pat. No. 5,726,588 to Fiedler, U.S. Pat. No. 55,606,268 to Van Brunt and U.S. Pat. No. 5,426,381 to Flannagan et al. None of these patents discloses or suggests the novel features of the present invention.